Blog
News and technical writing on synthetic, verified Verilog data.
Introducing p2v-training-batch-01: Chip Designs Where the Answer Is Already Known
A first look at p2v-training-batch-01: chip designs generated for LLM training and benchmarking, correct by construction, in many variations, each with exact ground truth.
Don't Collect Hardware Bugs. Generate Them.
Real bugs with verified root causes are rare. Python2Verilog (p2v) turns Python algorithms into many verified Verilog implementations, the raw material for training models to debug hardware.
Anatomy of a Hard Bug: What Root Cause Analysis Really Demands
What root cause analysis really demands in hardware debugging, why AI agents fail at it, and why the real bottleneck is data.
Your AI Can Write Verilog. Can It Debug It?
AI models can generate Verilog, but the real job in chip design is root cause analysis. Why debugging is the hard part, and why we built veriRCA to measure it.