Ask a modern AI model to write a Verilog module and you'll often get something impressive: clean, synthesizable, even well commented. Generation benchmarks are filling up with high scores, and it's tempting to conclude that AI for chip design is nearly solved.
It isn't. Writing a module is not where hardware teams spend their time.
The real job is figuring out why it broke
Anyone who has worked on a real chip knows the pattern. A test fails. A waveform shows the wrong value at some cycle. And then the actual work begins: finding out why.
That work is root cause analysis (RCA), and it is what separates a tool that demos well from a tool that helps ship silicon. Verification and debug consume a huge share of any chip project's effort. The 2018 Wilson Research Group study found that verification takes 53% of an average IC/ASIC project's time, and that verification engineers spend more of their time debugging (44%) than on any other task. More recent summaries of the 2024 reports put that figure at 47%. Much of that debugging effort is RCA.
Why RCA is hard
The difficulty has nothing to do with typing code. It comes from the distance between symptom and cause:
- 01
Distance in time
The output goes wrong at cycle 50,000, but the corruption began at cycle 400.
- 02
Distance in structure
The failing signal sits at the edge of the design, and the cause is buried several modules and pipeline stages upstream.
- 03
Distance in abstraction
The symptom is "the system hangs." The cause is a single wrong condition in a state machine.
Fixing what you can see is easy. Tracing causality backward, through logic you didn't write and state you can't directly observe, is the whole job.
Where agents struggle
This is exactly where today's AI agents tend to fall short. They patch the first mismatching signal instead of the underlying fault. They lean on patterns from designs they've seen before, and they stumble when the same logic is written in an unfamiliar style.
We can't improve what we don't measure
Most existing benchmarks don't really test this. Popular ones such as VerilogEval and RTLLM measure how well a model writes RTL, not how well it debugs it. The debugging benchmarks that do exist are small and mostly score whether a model produces a repair: CirFix offers 32 defect scenarios in which hardware experts seeded bugs into existing designs, and ChipBench includes 89 debugging cases built by manually injecting faults into golden modules. Models can memorize small sets of designs, and a lucky guess is indistinguishable from real understanding.
That is why I built veriRCA, a benchmark designed to test whether an agent can find the root cause of a hardware bug, not just guess a fix.